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| ? nec corporation 1994 description the m pd75117h is a 75x series 4-bit single-chip microcomputer. the m pd75117h is a product which has the same functions as those of the m pd751 f, with the minimum operating voltage reduced from the previous 2.7 v to 1.8 v, and achieving 1.91 m s operation at 1.8 v. there- fore, it facilitates low-voltage operation for a set requiring high-speed operation. functions are described in detail in the following users manual, which should be read when carrying out design work. m pd75117h users manual : ieu-799 features memory capacity rom : 24448 8 bits ( m pd75117h) : 16256 8 bits ( m pd75116h) ram : 768 4 bits high-speed low voltage operation minimum instruction execution time : 1.91 m s (v dd = 1.8 v) 0.95 m s (v dd = 2.7 v) operating voltage range : 1.8 to 5.5 v (t a = C40 to +60 c) input/output ports : 58 timer/counter : 3 channels ? timer/event counter 2 channels ? basic interval timer 1 channel 8-bit serial interface on chip programmable threshold port : 4-bit resolution 4 channels on-chip prom product available : m pd75p117h (one-time prom) applications cordless telephone subsets, portable radio equipment, pager, etc. 4-bit single-chip microcomputer mos integrated circuit m pd75116h,75117h data sheet document no. ic-3120 (o.d.no. ic-8502) date published may 1994p printed in japan the mark h shows major revised points. "unless there are any particular functional differences, the m pd75117h is described in this document as a representative product." the information in this document is subject to change without notice. h
2 m pd75116h,75117h ordering information ordering code package quality grade m pd75116hgc- -ab8 64-pin plastic qfp ( 14 mm) standard m pd75116hgk - -8a8 64-pin plastic qfp ( 12 mm) standard m pd75117hgc- -ab8 64-pin plastic qfp ( 14 mm) standard m pd75117hgk - -8a8 64-pin plastic qfp ( 12 mm) standard remarks : rom code number overview of functions contents 43 0.95 m s, 1.91 m s, 15.3 m s (4.19 mhz operation) 3-stage switching capability 24448 8 bits ( m pd75117h), 16256 8 bits ( m pd75116h) 768 4 bits 4 bits 8 4 banks (memory mapping) total 58 ? cmos input pins : 10 ? cmos input/output pins : 32 (pins with led direct drive capability *1 ) ? n-ch open-drain input/output pins : 12 (pins with led direct drive capability *2 ) (a pull-up resistor can be incorporated bit-wise.) ? comparator input pins (4-bit precision) : 4 ? 8-bit timer/event counter 2 ? 8-bit basic interval timer (watchdog timer applicable) ? 8 bits ? lsb-first/msb-first switchable ? 2 transfer modes (transmission/reception and dedicated reception modes) ? external : 3 ? internal : 4 ? external : 2 ? stop/halt mode ? various bit manipulation instructions (set, reset, test, boolean operation) ? 8-bit data transfer, comparison, operation, increment/decrement instructions ? 1-byte relative branch instruction ? geti instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte ? bit manipulation memory (bit sequential buffer: 16 bits) on chip ? 64-pin plastic qfp ( 14 mm) ? 64-pin plastic qfp ( 12 mm) item basic instructions instruction cycle on-chip memory general register input/output port timer/counter serial interface vectored interrupt test input standby instruction set others package rom ram *1. when v dd = 5 v, i ol = 15 ma. 2. when v dd = 5 v, i ol = 10 ma. h h h 3 m pd75116h,75117h differences between m pd75116h and m pd75117h m pd75116h m pd75117h 16256 8 bits 24448 8 bits (mask rom) (mask rom) 768 4 bits no yes memory bank 0 memory banks 0, 1, 2 2-byte stack 3-byte stack 3 machine cycles 4 machine cycles 2 machine cycles 3 machine cycles undefined operation normal operation sbs register stack area item rom ram stack stack operation when subroutine call instruction is executed call instruction machine cycle callf instruction machine cycle bra instruction calla instruction movt xa, bcde movt xa, bcxa br bcde br bcxa h 4 m pd75116h,75117h contents 1. pin configuration (top view) ...................................................................................................... 6 2. block diagram ................................................................................................................................... 8 3. pin functions ..................................................................................................................................... 9 3.1 port pins ....................................................................................................................................................... 9 3.2 other pins ..................................................................................................................................................... 10 3.3 pin input/output circuits ..................................................................................................................... 11 3.4 recommended connection of unused pins ................................................................................... 12 4. memory configuration ................................................................................................................. 13 5. peripheral hardware functions ............................................................................................... 18 5.1 port ................................................................................................................................................................. 18 5.2 clock generator ....................................................................................................................................... 19 5.3 clock output circuit ............................................................................................................................... 20 5.4 basic interval timer ................................................................................................................................ 21 5.5 timer/event counter ............................................................................................................................... 21 5.6 serial interface ......................................................................................................................................... 23 5.7 programmable threshold port (analog input port) .............................................................. 25 5.8 bit sequential buffer ............................................................................................................................. 26 6. interrupt function ........................................................................................................................ 27 7. standby function ............................................................................................................................ 29 8. reset function .................................................................................................................................. 30 9. instruction set ................................................................................................................................. 33 10. application example ....................................................................................................................... 43 10.1 cordless telephone (subset) .............................................................................................................. 43 10.2 display pager .............................................................................................................................................. 44 11. mask option selection ................................................................................................................... 45 12. electrical specifications ............................................................................................................. 46 13. package information ..................................................................................................................... 57 14. recommended soldering conditions ...................................................................................... 59 appendix a. functional differences among m pd751 series products ......................... 60 5 m pd75116h,75117h appendix b. development tools ........................................................................................................ 62 appendix c. related documents ........................................................................................................ 63 6 m pd75116h,75117h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p41 p42 p43 p30 p31 p32 p33 v dd ic* p140 p141 p142 p143 p130 p131 p132 p90 v ss p83 p82 p81 p80 p93 p92 p91 p13/int3 p12/int2 p11/int1 p10/int0 pth03 pth02 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p70 p71 p72 p73 p60 p61 p62 p63 x1 x2 reset p50 p51 p52 p53 p40 pth00 ti0 ti1 p23 p22/pcl p21/pto1 p20/pto0 p03/si p02/so p01/sck p00/int4 p123 p122 p121 p120 p133 pth01 1. pin configuration (top view) * connect the ic (internally connected ) pin to v dd directly. m pd75116hgc- -ab8 m pd75116hgk- -8a8 m pd75117hgc- -ab8 m pd75117hgk- -8a8 7 m pd75116h,75117h pin name p00-p03 : port 0 pcl : programmable clock output p10-p13 : port 1 sck : serial clock p20-p23 : port 2 so : serial data output p30-p33 : port 3 si : serial data input p40-p43 : port 4 pth00-pth03 : programmable treshold input p50-p53 : port 5 int0, int1, int4 : external vectored interrupt input 0, 1, 4 p60-p63 : port 6 int2, int3 : external test input 2, 3 p70-p73 : port 7 x1, x2 : system clock oscillation 1, 2 p80-p83 : port 8 reset : reset p90-p93 : port 9 v dd : positive power supply p120-p123 : port 12 v ss : ground p130-p133 : port 13 ic : internally connected p140-p143 : port 14 ti0, ti1 : timer input 0, 1 pto0, pto1 : programmable timer output 0, 1 8 m pd75116h,75117h 2. block diagram *1. the m pd75116h program counter is composed of 14 bits. 2. the m pd75117h incorporates the sbs register. p ort 0 port 1 4 4 p00-p03 p10-p13 port 3 port 4 port 5 port 6 4 4 4 4 port 2 4 p20-p23 p30-p33 p40-p43 p50-p53 p60-p63 port 7 4 p70-p73 sp(8) bank general reg. ram data memory 768 4 bits decode and control cy alu program counter (15) *1 rom program memory 16256 8 bits : pd75116h 24448 8 bits : pd75117h reset v ss stand by control v dd cpu clock clock generator clock divider clock output control x2 x1 pcl/p22 f x / 2 n basic interval timer inter- rupt control intt1 intbt port 14 4 p140-p143 port 12 4 p120-p123 timer/event counter #0 intt0 ti0 pto0/p20 timer/event counter #1 ti1 pto1/p21 serial interface intsio sck/p01 so/p02 si/p03 program- mable threshold port #0 pth00-pth03 int4/p00 int2/p12 int1/p11 int0/p10 int3/p13 port 13 4 p130-p133 port 9 4 p90-p93 port 8 4 p80-p83 bit seq. buffer (16) sbs(2) *2 4 f m m 9 m pd75116h,75117h 3. pin functions 3.1 port pins dual- function pin int4 sck so si int0 int1 int2 int3 pto0 pto1 pcl i/o circuit type *1 b f e b b e e e e e e e e m m m *1. : schmitt trigger input 2. direct led drive capability (when v dd = 5 v, i ol = 15 ma). 3. direct led drive capability (when v dd = 5 v, i ol = 10 ma). 4. open-drain high impedance on-chip pull-up resistor high level *3 *3 *2 *2 *2 *2 *2 *2 *2 *2 *3 h h pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to p83 p90 to p93 p120 to p123 p130 to p133 p140 to p143 input/output input input/output input/output input input input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output function 4-bit input port (port 0). 4-bit input port (port 1). 4-bit input/output port (port 2). programmable 4-bit input/output port (port 3). input/output can be specified bit-wise. 4-bit input/output port (port 4). 4-bit input/output port (port 5). programmable 4-bit input/output port (port 6). input/output can be specified bit-wise. 4-bit input/output port (port 7). 4-bit input/output port (port 8). 4-bit input/output port (port 9). n-ch open-drain 4-bit input/output port (port 12). on-chip pull-up resistor can be specified bit- wise (mask option). open-drain: +6 v withstand voltage n-ch open-drain 4-bit input/output port (port 13). on-chip pull-up resistor can be specified bit- wise (mask option). open-drain: +6 v withstand voltage n-ch open-drain 4-bit input/output port (port 14). on-chip pull-up resistor can be specified bit- wise (mask option). open-drain: +6 v withstand voltage 8-bit i/o reset input input input input input input input input input input input *4 input *4 input *4 10 m pd75116h,75117h 3.2 other pins dual- function pin p20 p21 p01 p02 p03 p00 p10 p11 p12 p13 p22 i/o circuit type *1 n b e f e b b b b e b * : schmitt trigger input pin name pth00 to pth03 ti0 ti1 pto0 pto1 sck so si int4 int0 int1 int2 int3 pcl x1, x2 reset ic v dd v ss input/output input input input/output input/output input/output input input input input input/output input input function variable threshold voltage 4-bit analog input port. external event pulse input to timer/event counter. or edge detection vectored interrupt input, or 1-bit input is also possible. timer/event counter output. serial clock input/output. serial data output. serial data input. edge detection vector interrupt input (detection of both rising and falling edges) edge detection vector interrupt input (detection edge selectable) edge detection test input (rising edge detection) clock output system clock oscillation crystal/ceramic connection pin. when an external clock is used, the clock is input to x1 and the inverted clock is input to x2. system reset input (low-level active). internally connected. ic pin should be connected to v dd directly. positive power supply. gnd potential. reset input input input input input input input input 11 m pd75116h,75117h 3.3 pin input/output circuits the input/output circuits of each pin of the m pd75117h are shown by in abbreviated form. fig. 3-1 pin input/output circuit list type a type f type b type d type e type m type n in/out data output disable type d p-ch v dd in n-ch in pull-up resistor v dd in/out n-ch (+6 v withstand voltage) data output disable (mask option) middle-high voltage input buffer (+6 v withstand voltage) in/out data output disable type d type a p-ch v dd out n-ch data output disable + v ref (threshold voltage) cmos standard input buffer this is an input/output circuit made up of a type d push-pull output and type b schmitt-triggered input. schmitt-trigger input with hysteresis characteristic push-pull output that can be made high- impedance output (p-ch and n-ch off) this is an input/output circuit made up of a type d push-pull output and type a input buffer. comparator type b 12 m pd75116h,75117h 3.4 recommended connection of unused pins pin pth00 to pth03 ti0 ti1 p00 p01 to p03 p10 to p13 p20 to p23 p30 to p33 p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to p83 p90 to p93 p120 to p123 p130 to p133 p140 to p143 ic recommended connection connect to v ss or v dd . connect to v ss . connect to v ss or v dd . connect to v ss . input status : connect to v ss or v dd . output status : leave open. connect to v dd directly. 13 m pd75116h,75117h 4. memory configuration program memory (rom) : 24448 8 bits (0000h to 5f7fh) : m pd75117h 16256 8 bits (0000h to 3f7fh) : m pd75116h ? 0000h, 0001h : vector table in which a program start address after reset is written. ? 0002h to 000bh : vector table in which program start addresses after interruption are written. ? 0020h to 007fh : table area referred by geti instruction data memory ? data area : 768 4 bits (000h to 2ffh) ? peripheral hardware area : 128 4 bits (f80h to fffh) 14 m pd75116h,75117h note since the above interrupt vector start address is a 14-bit address, set it in a 16k space (0000h to 3fffh). remarks apart from the above instructions, branching is possible to an address at which only the pc low- order 8 bits have been changed by the br pcde or br pcxa instruction. fig. 4-1 program memory map (1/2) (a) m pd75117h ? ? ? ? ? ? ? mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 7 6 0 address internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) int0/int1 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0/int1 start address (low-order 8 bits) intsio start address (high-order 6 bits) intsio start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intt1 start address (high-order 6 bits) intt1 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br !addr instruction branch address ? rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe 1fffh 2000h 2fffh 3000h 3fffh 4000h 4fffh 5000h 5f7fh ? ? ? ? ? ? ? ? call !addr instruction branch address branch/call address by geti br bcde br bcxa branch address bra !addr1 instruction branch address calla !addr1 instruction branch address br $addr1 instruction relative branch address (-15 to -1, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 15 m pd75116h,75117h fig. 4-1 program memory map (2/2) (b) m pd75116h mbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 76 0 address internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) int0/int1 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0/int1 start address (low-order 8 bits) intsio start address (high-order 6 bits) intsio start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intt1 start address (high-order 6 bits) intt1 start address (low-order 8 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br ! addr instruction branch address rbe mbe rbe mbe rbe mbe rbe mbe rbe mbe rbe 1fffh 2000h 2fffh 3000h 3f7fh call ! addr instruction subroutine entry address br $ addr instruction relative branch address ?5 to ?, +2 to +16 branch destination address and subroutine entry address by geti instruction brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address remarks apart from the above instructions, branching is possible to an address at which only the pc low- order 8 bits have been changed by the br pcde or br pcxa instruction. 16 m pd75116h,75117h fig. 4-2 data memory map (1/2) (a) m pd75117h 256 4 256 4 256 4 128 4 (32 4) bank 0 bank 1 bank 15 000h 01fh 020h 0ffh 100h 1ffh 200h 2ffh f80h fffh general register area stack area data area static ram (768 4) peripheral hardware area data memory memory bank not on-chip bank 2 17 m pd75116h,75117h fig. 4-2 data memory map (2/2) (b) m pd75116h 256 4 256 4 256 4 128 4 (32 4) bank 0 bank 1 bank 15 000h 01fh 020h 0ffh 100h 1ffh 200h 2ffh f80h fffh general register area stack area data area static ram (768 4) peripheral hardware area data memory memory bank not on-chip bank 2 18 m pd75116h,75117h 5. peripheral hardware functions 5.1 port there are the following three digital input/output ports. ? cmos input (port0, port1) : 8 ? cmos input/output (port2 to port9) : 32 ? n-ch open-drain input/output (port12 to port14) : 12 total : 52 table 5-1 port function port name function operation/features remarks 4-bit input 4-bit input/output 4-bit input/output (n-ch open-drain +6 v withstand voltage) regardless of the operating mode of the shared pin, reading or test is always possible. can be set in the input or output bit-wise. can be set in the input or output mode as a 4- bit unit. ports 4 and 5, 6 and 7, and 8 and 9 are paired and data input/output is possible as an 8-bit unit. can be set to input or output mode as a 4-bit unit. ports 12 and 13 are paired and data input/ output is possible as an 8-bit unit. these pins are shared with si, so, sck, int0 to int4. port 2, pto0, pto1, and pcl share the same pins. on-chip pull-up resistor specifi- able bit-wise by mask option. port 0 port 1 port 3 *1 port 6 *1 port 2 *1 port 4 *1 port 5 *1 port 7 *1 port 8 *1 port 9 *1 port12 *2 port13 *2 port14 *2 *1. when v dd = 5 v, i ol = 15 ma. 2. when v dd = 5 v, i ol = 10 ma. h h 19 m pd75116h,75117h 5.2 clock generator the clock generator operation is determined by the processor clock control register (pcc). this circuit can also change the instruction execution time. 0.95 m s/1.91 m s/15.3 m s (4.19 mhz operation) fig. 5-1 clock generator block diagram * instruction execution remarks 1. f xx = crystal/ceramic oscillator frequency 2. f x = external clock frequency 3. f = cpu clock 4. pcc : processor clock control register 5. one f clock cycle (t cy ) is one machine cycle. see "ac characteristics" in 12. "electrical specifications" for t cy . h x1 f xx or f x ?basic interval timer (bt) ?clock output circuit ?timer/event counter ?serial interface frequency divider 1/2 selector halt f/f wait release signal from bt reset signal (internal reset) standby release signal from interrupt control circuit stop f/f s r q pcc2, pcc3 clear oscillation stop pcc 4 internal bus system clock oscillation circuit s r q halt * stop * frequency divider 1/4 ?cpu ?clock output circuit f 1/16 x2 1/8 to 1/4096 pcc0 pcc1 pcc2 pcc3 20 m pd75116h,75117h 5.3 clock output circuit the clock output circuit is a circuit which outputs a clock pulse from p22/pcl and is used to supply clock pulses to remote control outputs or peripheral lsis. clock output (pcl) : f , 524 khz, 262 khz (4.19 mhz operation) fig. 5-2 configuration of clock output circuit clom3 clom1 clom0 4 internal bus clom p22 output latch port2.2 bit 2 of pmgb bit specified in port 2 input/output mode output buffer pcl/p22 f xx /2 3 f xx /2 4 selector f from clock generator clom2 21 m pd75116h,75117h 5.4 basic interval timer the basic interval timer includes the following functions. it operates as an interval timer which generates reference time interrupts. it can be applied as a watchdog timer which detects when a program is out of control. selects and counts wait times when the standby mode is released. it reads count contents. fig. 5-3 basic interval timer configuration * set1 indicates instruction execution. 5.5 timer/event counter the m pd75117h incorporates two internal timer/event counter channels. timer/event counter channel 0 and channel 1 differ only in selectable count pulse (cp) and clock supply function to serial interface and are the same in other configurations and functions. operates as a programmable interval timer. outputs square waves in the desired frequency to the pton pin. operates as an event counter. use of tin pin as an external interrupt input pin. divides the tin pin input into n divisions and outputs it to the pton pin (frequency divider operation). supplies a serial shift clock to the serial interface circuit. (channel 0 only) count status read function. internal bus f xx /2 5 f xx /2 7 f xx /2 12 from clock generator 4 btm3 btm2 btm1 btm0 btm mpx bt irqbt set bt interrupt request flag clear clear basic interval timer (8-bit frequency divider) wait release signal during standby release 8 3 vector interrupt request signal f xx /2 9 set1 * 22 m pd75116h,75117h fig. 5-4 timer/event counter block diagram (n = 0, 1) * set1 : instruction execution. from clock generator input buffer mpx tmn6 set1 *1 tmn timer operation start cp count register (8) clear 8 comparator (8) 8 8 modulo register (8) 8 8 internal bus tmodn match tout f/f toen to enable flag p2n output latch port2.n bit 2 of pgmb port 2 input/ output mode to serial interface (channel 0 only) p2n/pton output buffer inttn ? irqtn set ? signal ? irqtn clear signal tn tin tin tmn7 tmn5 tmn4 tmn3 tmn2 tmn1 tmn0 ton to selector edge detector tmn0 reset tmn1 tofn 23 m pd75116h,75117h 5.6 serial interface the serial interface has the following functions. clock 8-bit transmission/reception operation (simultaneous transmission/reception) clock 8-bit reception operation (so output high impedance) half-duplex asynchronous transfer (software control) lsb-first/msb-first switchable these functions facilitate serial bus data communications with other computers such as m pd7500 series, 78k series, etc., or conjunction with a peripheral device. 24 m pd75116h,75117h * set1 : instruction execution fig. 5-5 serial interface block diagram shift registor (8) serial clock counter (3) clear overflow serial start siom7 siom6 siom5 siom4 siom3 siom2 siom1 siom0 siom set1 * 8 8 8 p03/si p02/so p01/sck sio7 sio sio0 intsio ? irqsio ? set signal ? irqsio clear signal tof0 (from timer channel 0) f xx /2 10 f xx /2 4 j mpx r s q internal bus 25 m pd75116h,75117h 5.7 programmable threshold port (analog input port) the m pd75117h is provided with 4-bit analog input pins (pth00 to pth03) for which the threshold voltage can be changed. these pins have a configuration as shown in fig. 5-6. the threshold voltage (v ref ) can be selected in 16 ways (v dd C v dd ) and analog signals can be directly input. this port can also be used as a digital signal input port by selecting v dd as v ref . fig. 5-6 programmable threshold port block diagram 16 16 0.5 15.5 7.5 16 h pthm7 pthm6 pthm5 pthm4 pthm3 pthm2 pthm1 pthm0 pthm 4 mpx v ref v dd pth00 pth01 pth02 pth03 + + + + operation stopped pth0 input buffer programmable threshold port input latch (4) internal bus 8 2 1 r 2 1 r r r 26 m pd75116h,75117h 5.8 bit sequential buffer 16 bits bit manipulation of the bit sequential buffer is the bit manipulation special data memory. since, in particular, the bit manipulation can easily be performed by changing sequentially address and bit specification, it is convenient when processing data comprising a large number of bits bit-wise. fig. 5-7 bit sequential buffer format remarks in pmem. @l addressing, the specified bit moves according to the l register. 321032 1 0 32103210 l = 0 l = 3 l = 4 decs l l = 7 l = 8 incs l l = b l = c l = f fc3h fc2h fc1h fc0h symbol address l register bsb3 bsb2 bsb1 bsb0 bit 27 m pd75116h,75117h 6. interrupt function the m pd75117h has 7 interrupt sources. multiple interrupts with priority is are also possible. two test sources are also provided. the test sources are edge detection testable inputs. table 6-1 interrupt sources intbt (standard time interval signal from basic interval timer) int4 (both rising edge and falling edge detection) int0 int1 intt0 (match signal from timer/event counter# 0 or ti0 input edge detection) intt1 (match signal from timer/event counter# 1 or ti1 input edge detection) int2 *2 (rising edge detection) int3 *2 (rising edge detection) vector interrupt request signal (vector table address) (rising edge and falling edge detection selection) internal external 1 2 interrupt order *1 internal/external interrupt source external external vrq1 (0002h) vrq3 (0006h) intsio (serial data transfer end signal) internal internal/external internal/external 3 4 5 vrq4 (0008h) vrq5 (000ah) vrq2 (0004h) external testable input signal (set irq2 and irq3) *1. the interrupt order is the priority order when multiple interrupt requests are generated simultaneously. 2. int2 and int3 are of test sources . these are affected by interrupt enable flags in the same way as interrupt sources, but do not generate vector interrupts. the m pd75117h interrupt control circuit has the following functions: hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (ie ) and interrupt master enable flag (ime). arbitrary setting of interrupt start address. multiple interruption function by which priority can be specified using the interrupt priority selection register (ips). interrupt request flag (irq ) test function (interrupt generation confirmation by software possible). standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible). 28 m pd75116h,75117h fig. 6-1 interrupt control circuit block diagram 22 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 int2 /p12 irq4 irq0 irq1 irqsio irqt0 irqt1 irq2 int bt intsio intt0 intt1 (ime) ist internal bus vector table address generator priority control circuit standby release signal interrupt enable flag (ie xxx ) edge detection circuit edge detection circuit decoder ips 42 int3 /p13 edge detection circuit edge detection circuit interrupt request flag 9 irq3 edge detection circuit 29 m pd75116h,75117h 7. standby function to reduce the power consumption during program wait, the m pd75117h has two standby modes (stop mode and halt mode). table 7-1 standby mode setting and operation status interrupt request signal from operable hardware enabled by interrupt enable flag, or reset input stop mode stop instruction system clock oscillation stopped operation possible only when the external sck input and to0 output (when timer/event counter 0 is external ti0 input) are selected as a serial clock operable only when tin pin input specified as count clock operation stopped operation of int0 to int4 possible operation stopped setting instruction clock generator basic interval timer operation status halt mode halt instruction only cpu clock f stopped operable (irqbt set at reference time intervals) operation possible if a clock other than f is specified as a serial clock except cpu clock f , output possible. operation stopped serial interface timer/event counter clock output circuit external interrupt cpu operation possible release signal operation stopped 30 m pd75116h,75117h 8. reset function the reset operation timing is shown in fig. 8-1. fig. 8-1 reset operation by reset input wait (31.3 ms/4.19 mhz) halt mode operating mode internal reset operation operating mode or standby mode reset input the state of hardware after reset operation is as shown in table 8-1. 31 m pd75116h,75117h reset input in standby mode table 8-1 status of each hardware after resetting (1/2) reset input during operation low-order 6 bits of program memory address 0000h are set in pc 13 to pc 8 and the contents of address 0001h are set in pc 7 to pc 0 . pc 14 *1 is set to 0. undefined 0 0 sets program memory address 000h bit 6 and bit 7 to rbe and mbe, respectively. undefined undefined undefined undefined 0, 0 low-order 6 bits of program memory address 0000h are set in pc 13 to pc 8 and the contents of address 0001h are set in pc 7 to pc 0 . pc 14 *1 is set to 0. undefined 0 0 ffh 0 0, 0 held 0 0 0 held 0 0 sets program memory address 000h bit 6 and bit 7 to rbe and mbe, respec- tively. undefined undefined held *2 held 0, 0 basic interval timer timer/event counter (n = 0, 1) serial interface clock generator, clock output circuit counter (bt) mode register (btm) counter (tn) modulo register (tmodn) mode register (tmn) toen, tofn shift register (sio) mode register (siom) processor clock control register (pcc) clock output mode register (clom) undefined 0 0 ffh 0 0, 0 undefined 0 0 0 hardware program counter (pc) carry flag (cy) skip flag (sk0 to sk2) psw interrupt status flag (ist0, ist1) bank enable flag (mbe, rbe) stack pointer (sp) stack bank selection register (sbs) *1 data memory (ram) general register (x, a, h, l, d, e, b, c) bank selection register (mbs, rbs) *1. compatible with the m pd75117h only. 2. data of data memory addresses 0f8h to 0fdh becomes undefined by reset input. 32 m pd75116h,75117h table 8-1 status of each hardware after resetting (2/2) reset input during operation hardware reset input in standby mode interrupt request flag (irq ) interrupt enable flag (ie ) priority selection register (ips) int0, int1 mode registers (im0, im1) output buffer output latch i/o mode register (pmga, pmgb, pmgc) pth00 to pth03 input latch mode register (pthm) undefined 0 0 0 0, 0 undefined 0 0 0 0, 0 interrupt function irq1,irq2, irq4 other than above off clear (0) 0 undefined 0 0 digital port analog port bit sequential buffer (bsb0 to bsb3) off clear (0) 0 undefined 0 0 h 33 m pd75116h,75117h identifier description reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp' xa, bc, de, hl, xa', bc', de', hl' rp'1 bc, de, hl, xa', bc', de', hl' rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label * bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label m pd75116h 0000h to 3f7fh immediate data or label m pd75117h 0000h to 3fffh immediate data or label addr1 0000h to 5f7fh immediate data or lebel caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (however, bit0 = 0) or label portn port 0 to port 9, port12 to port14 ie iebt, iesio, iet0, iet1, ie0 to ie4 rbn rb0 to rb3 mbn mb0, mb1, mb2, mb15 9. instruction set (1) operand identifier and description the operand is described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (for details, refer to ra75x assembler package users manual language volume (eeu-730) .) when there are multiple elements in the description, one of the elements is selected. upper case letters and symbols (+,C) are keywords and are described unchanged. various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (for details, refer to m pd75117h users manual (ieu-799) .) however, there are restrictions on the labels for which fmem and pmem can be used. * in the case of the 8-bit data processing, an even address only can be described for mem. addr 34 m pd75116h,75117h (2) operation description legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa' : extension register pair (xa') bc' : extension register pair (bc') de' : extension register pair (de') hl' : extension register pair (hl') pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : portn (n = 0 to 9, 12 to 14) ime : interrupt master enable flag ips : interrupt priority selection register ie : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : address, bit delimiter ( ) : contents addressed by h : hexadecimal data 35 m pd75116h,75117h (3) description of addressing area field symbols *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 mb = mbe ? mbs (mbs = 0, 1, 2, 15) mb = 0 mbe = 0 : mb = 0 (00h to 7fh) mb = 15 (80h to ffh) mbe = 0 : mb = mbs (mbs = 0, 1, 2, 15) mb = 15, fmem = fb0h to fbfh, ff0h to fffh mb = 15, pmem = fc0h to fffh addr = 0000h to 3f7fh ( m pd75116h) 0000h to 3fffh ( m pd75117h) ? m pd75116h addr = (current pc) C15 to (current pc) C1, (current pc) + 2 to (current pc) + 16 ? m pd75117h addr1 = (current pc) C15 to (current pc) C1, (current pc) + 2 to (current pc) + 16 caddr = 0000h to 0fffh (pc 13, 12 = 00b : m pd75116h) = 0000h to 0fffh (pc 14, 13, 12 = 000b : m pd75117h) = 1000h to 1fffh (pc 13, 12 = 01b : m pd75116h) = 1000h to 1fffh (pc 14, 13, 12 = 001b : m pd75117h) = 2000h to 2fffh (pc 13, 12 = 10b : m pd75116h) = 2000h to 2fffh (pc 14, 13, 12 = 010b : m pd75117h) = 3000h to 3f7fh (pc 13, 12 = 11b : m pd75116h) = 3000h to 3fffh (pc 14, 13, 12 = 011b : m pd75117h) = 4000h to 4fffh (pc 14, 13, 12 = 100b : m pd75117h) = 5000h to 5f7fh (pc 14, 13, 12 = 101b : m pd75117h) faddr = 0000h to 07ffh taddr = 0020h to 007fh addr1 = 0000h to 5f7fh ( : m pd75117h only) data memory addressing ????? remarks 1. mb indicates the accessible memory bank. 2. for *2, mb = 0 without regard to mbe and mbs. 3. for *4 and *5, mb = 15 without regard to mbe and mbs. 4. *6 to *10 indicate the addressable area. program memory addressing ????? ??????????????? ??????????????? 36 m pd75116h,75117h (4) explanation of machine cycle field s shows the number of machine cycles required when skip is performed by an instruction with skip. the value of s changes as follows: ? no skip ....................................................................................................................................................................... s = 0 ? when instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... s = 1 ? when instruction to be skipped is 3-byte instruction .......................................................................................... s = 2 (br !addr, bra !addr1 * , call !addr, calla !addr1 * instructions) * this instruction is valid for the m pd75117h only. note one machine cycle is required to skip a geti instruction. one machine cycle is equivalent to one cycle (= t cy ) of the cpu clock f . three times can be selected by pcc setting. 37 m pd75116h,75117h a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg xa, rp' reg1, a rp'1, xa a, @hl a, @hl+ a, @hl- a, @rpa1 xa, @hl a, mem xa, mem a,reg1 xa, rp' xa, @pcde xa, @pcxa xa, @bcde * xa, @bcxa * 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 a ? n4 reg1 ? n4 xa ? n8 hl ? n8 rp2 ? n8 a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l C 1 a ? (rpa1) xa ? (hl) (hl) ? a (hl) ? xa a ? (mem) xa ? (mem) (mem) ? a (mem) ? xa a ? reg xa ? rp' reg1 ? a rp'1 ? xa a ? (hl) a ? (hl), then l ? l + 1 a ? (hl), then l ? l C 1 a ? (rpa1) xa ? (hl) a ? (mem) xa ? (mem) a ? reg1 xa ? rp' xa ? (pc 13-8 + de) rom xa ? (pc 14-8 + de) rom xa ? (pc 13-8 + xa) rom xa ? (pc 14-8 + xa) rom xa ? (b 2-0 + cde) rom xa ? (b 2-0 + cxa) rom skip condition stack a stack a stack b l = 0 l = fh l = 0 l = fh *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *1 *1 *2 *1 *3 *3 *11 *11 transfer table reference mnemonic operands bytes machine cycles operation instruction group addressing area xch mov movt 1 2 2 2 2 1 2 + s 2 + s 1 2 1 2 2 2 2 2 2 2 2 2 1 2 + s 2 + s 1 2 2 2 1 2 3 3 3 3 * the 3 lower bits in the b register are valid only. remarks shading indicates a part compatible with the m pd75117h. 38 m pd75116h,75117h cy, fmem.bit cy, pmem.@l cy, @h+mem.bit fmem.bit, cy pmem.@l, cy @h+mem.bit, cy a, #n4 xa, #n8 a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa a, #n4 a, @hl xa, rp' rp'1, xa cy ? (fmem.bit) cy ? (pmem 7 C 2 + l 3 C 2 .bit(l 1C0 )) cy ? (h + mem 3 C 0 .bit) (fmem.bit) ? cy (pmem 7 C 2 + l 3 C 2 .bit(l 1C0 )) ? cy (h + mem 3 C 0 .bit) ? cy a ? a + n4 xa ? xa + n8 a ? a + (hl) xa ? xa + rp' rp'1 ? rp'1 + xa a, cy ? a + (hl) + cy xa, cy ? xa + rp' + cy rp'1, cy ? rp'1 + xa + cy a ? a C (hl) xa ? xa C rp' rp'1, cy ? rp'1 C xa C cy a, cy ? a C (hl) C cy xa, cy ? xa C rp' C cy rp'1, cy ? rp'1 C xa C cy a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa a ? a n4 a ? a (hl) xa ? xa rp' rp'1 ? rp'1 xa skip condition operands bytes machine cycles operation addressing area *4 *5 *1 *4 *5 *1 *1 *1 *1 *1 *1 *1 *1 carry carry carry carry carry borrow borrow borrow instruction group mnemonic mov1 bit transfer adds 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 addc subc and operations 2 2 2 2 2 2 1 + s 2 + s 1 + s 2 + s 2 + s 1 2 2 1 + s 2 + s 2 + s 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 subs or xor 39 m pd75116h,75117h a a reg rp1 @hl mem reg rp' reg, #n4 @hl, #n4 a, @hl xa, @hl a, reg xa, rp' cy cy cy cy mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit mem.bit fmem.bit pmem.@l @h + mem.bit fmem.bit pmem.@l @h + mem.bit operands operation instruction group mne- monic bytes 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 machine cycles cy a 0 , a 3 cy, a nC1 a n a a reg reg + 1 rp1 rp1 + 1 (hl) (hl) + 1 (mem) (mem) + 1 reg reg C 1 rp' rp' C 1 skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if xa = (hl) skip if a = reg skip if xa = rp' cy 1 cy 0 skip if cy = 1 cy cy (mem.bit) 1 (fmem.bit) 1 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 1 (h + mem 3C0 .bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem 7C2 + l 3C2 .bit (l 1C0 )) 0 (h + mem 3C0 .bit) 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 skip if (h + mem 3C0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 0 skip if (h + mem 3C0 .bit) = 0 skip if (fmem.bit) = 1 and clear skip if (pmem 7C2 + l 3C2 .bit (l 1C0 )) = 1 and clear skip if (h + mem 3C0 .bit) = 1 and clear addressing area skip condition reg = 0 rp1 = 00h (hl) = 0 (mem) = 0 reg = fh rp' = ffh reg = n4 (hl) = n4 a = (hl) xa = (hl) a = reg xa = rp' cy = 1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 1 2 1 + s 1 + s 2 + s 2 + s 1 + s 2 + s 2 + s 2 + s 1 + s 2 + s 2 + s 2 + s 1 1 1 + s 1 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s rorc *1 *3 *1 *1 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 ske comparison set1 clr1 skt not1 carry flag manipulation set1 memory bit manipulation clr1 skt skf sktclr accumulator manipulation not incs increment /decrement decs 40 m pd75116h,75117h instruction group mne- monic branch bytes machine cycles addressing area skip condition operation operands *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 *11 *6 *7 *11 *11 *11 *8 *6 and1 memory bit manipulation xor1 2 2 2 2 2 2 2 2 2 3 2 2 3 3 3 3 3 2 3 4 or1 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 3 2 3 br brcb bra subroutine stack control call cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit cy, fmem.bit cy, pmem.@l cy, @h + mem.bit addr *1 addr1 !addr $addr $addr1 pcde pcxa bcde *2 bcxa *2 !addr1 !caddr !addr *1. m pd75116h only. 2. the 3 lower bits in the b register are valid only. remarks shading indicates a part compatible with the m pd75117h. cy ? cy (fmem.bit) cy ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy (h + mem 3C0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy (h + mem 3C0 .bit) cy ? cy (fmem.bit) cy ? cy (pmem 7C2 + l 3C2 .bit (l 1C0 )) cy ? cy (h + mem 3C0 .bit) pc 13C0 ? addr (the assembler selects the optimum in- struction from among the br !addr, brcb !caddr, and br $addr instructions.) pc 14C0 ? addr1 (the assembler selects the optimum in- struction from among the br !addr, bra !addr1, brcb !caddr, and br $addr1 in- structions.) pc 13-0 ? addr pc 14-0 , pc 13-0 ? addr pc 13-0 ? addr pc 14-0 ? addr1 pc 13-0 ? pc 13-8 + de pc 14-0 ? pc 14-8 + de pc 13-0 ? pc 13-8 + xa pc 14-0 ? pc 14-8 + xa pc 14-0 ? b 2-0 + cde pc 14-0 ? b 2-0 + cxa pc 14-0 ? !addr1 pc 13-0 ? pc 13,12 + caddr 11-0 pc 14-0 ? pc 14,13,12 + caddr 11-0 (sp C 4) (sp C 1) (sp C 2) ? pc 11-0 (sp C 3) ? mbe, rbe, pc 13 , pc 12 pc 13-0 ? addr, sp ? spC4 (sp C 2) ? , , mbe, rbe (sp C 6) (sp C 3) (sp C 4) ? pc 11-0 (sp C 5) ? 0, pc 14 , pc 13 , pc 12 pc 14 ? 0, pc 13-0 ? addr, sp ? spC6 41 m pd75116h,75117h (sp C 2) , , mbe, rbe (sp C 6) (sp C 3) (sp C 4) pc 11-0 (sp C 5) 0, pc 14 , pc 13 , pc 12 pc 14C0 addr1, sp spC6 (sp C 4) (sp C 1) (sp C 2) pc 11C0 (sp C 3) mbe, rbe, pc 13 , pc 12 pc 13C0 000 + faddr, sp sp C 4 (sp C 2) , , mbe, rbe (sp C 6) (sp C 3) (sp C 4) pc 11C0 (sp C 5) 0, pc 14 , pc 13 , pc 12 pc 14C0 0000 + faddr, sp sp C 6 mbe, rbe, pc 13 , pc 12 (sp + 1) pc 11C0 (sp) (sp + 3) (sp + 2) sp sp + 4 pc 11C0 (sp) (sp + 3) (sp + 2) , pc 14 , pc 13 , pc 12 (sp + 1) , , mbe, rbe (sp + 4) sp sp +6 mbe, rbe, pc 13 , pc 12 (sp + 1) pc 11C0 (sp) (sp + 3) (sp + 2) sp sp + 4, then skip unconditionally pc 11C0 (sp) (sp + 3) (sp + 2) , pc 14 , pc 13 , pc 12 (sp + 1) , , mbe, rbe (sp + 4) sp sp +6 then skip unconditionally pc 13 , pc 12 (sp + 1) pc 11C0 (sp) (sp + 3) (sp + 2) psw (sp + 4) (sp + 5), sp sp +6 pc 11C0 (sp) (sp + 3) (sp + 2) , pc 14 , pc 13 , pc 12 (sp + 1) psw (sp + 4) (sp + 5), sp sp +6 (sp C 1) (sp C 2) rp, sp sp C 2 (sp C 1) mbs, (sp C 2) rbs, sp sp C 2 rp (sp + 1) (sp), sp sp + 2 mbs (sp + 1), rbs (sp), sp sp + 2 ime (ips.3) 1 ie 1 ime (ips.3) 0 ie 0 operation instruction group mne- monic skip condition operands bytes machine cycles addressing area subroutine stack control push pop ei di rp bs rp bs ie ie 1 2 1 2 2 2 2 2 1 2 1 2 2 2 2 2 interrupt control calla !addr1 3 3 *11 *9 callf !faddr 2 2 3 1 ret unconditional 3 + s 1 rets 3 1 reti remarks shading indicates a part compatible with the m pd75117h. 3 42 m pd75116h,75117h operation instruction group mne- monic skip condition operands addressing area ------------------------ bytes machine cycles 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 1 2 2 a ? portn (n = 0 to 9, 12 to 14) xa ? portn + 1 , portn (n = 4, 6, 8, 12) portn ? a (n = 2 to 9, 12 to 14) portn + 1 , portn ? xa (n = 4, 6, 8, 12) set halt mode (pcc.2 ? 1) set stop mode (pcc.3 ? 1) no operation rbs ? n (n = 0 to 3) mbs ? n (n = 0, 1, 2, 15) ? tbr instruction pc 13C0 ? (taddr) 5C0 ? (taddr + 1) pc 14 ? 0 ? tcall instruction (sp C 5) (sp C 6) (sp C 3)(sp C 4) ? pc 14C0 (sp C 2) ? ( , , mbe, rbe) pc 13C0 ? (taddr) 5C0 ? (taddr + 1) sp ? sp C 6 pc 14 ? 0 ? other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) ? tbr instruction pc 13C0 ? (taddr) 5C0 ? (taddr + 1) pc 14 ? 0 ? tcall instruction (sp C 5) (sp C 6) (sp C 3)(sp C 4) ? , pc 14C0 (sp C 2) ? , , mbe, rbe pc 13C0 ? (taddr) 5C0 ? (taddr + 1) sp ? sp C 6, pc 14 ? 0 ? other than tbr and tcall instruction execution of an instruction addressed at (taddr) and (taddr + 1) a, portn xa, portn portn, a portn, xa rbn mbn *1 halt stop nop in *1 out input/output cpu control sell taddr *2 geti special ----------------------- conforms to referenced instruction. conforms to referenced instruction. ------------------------ ------------------------------------------------------------------------ ------------------------------------------------------------------------ 3 3 4 *10 1 *10 1 ------------------------ ------------------------------------------------------------------------ ------------------------------------------------------------------------ 4 3 3 remarks shading indicates a part compatible with the m pd75117h. *1. when executing the in/out instruction, 43 m pd75116h,75117h 10. application example 10.1 cordless telephone (subset) legend idc : immediate deviation controller, id rom : id (identification) code rom, lcd : liquid crystal display led : light emitting diode, mpx : multiplexer msk : minimum shift keying pll : phase locked loop, sio : serial data input/output tcxo : temperature compensation crystal oscillator vco : voltage control oscillator power amp idc amp compres- sion transmitter/ receiver extension mpx msk modem speaker speaker amp led display key matrix led display lcd controller/ driver console detection id rom sio radio wave detection extra-area detection tcxo pll vco prescaler pll vco prescaler mpx mixer 2sc4226 3sk177 filter amp 2sc2757 2sc4182 pd6252 pd7228 pd7511h m m m 44 m pd75116h,75117h 10.2 display pager filter int to code rom piezoelectric buzzer comparator input high-current output led display switch ram battery check lcd display lcd controller/driver sio pd75117h pd7228/7229 m m 45 m pd75116h,75117h 11. mask option selection the m pd75117h has the following mask option. pin function mask option pull-up resistor (can be specified bit-wise.) no pull-up resistor (can be specified bit-wise.) p12 to p14 46 m pd75116h,75117h supply voltage C0.3 to +7.0 v v i1 v i2 *1 v o i oh i ol *2 t opt t stg v dd C40 to +60 c C65 to +150 c output current high 12. electrical specifications absolute maximum ratings (ta = 25 c) parameter symbol test conditions rating unit except ports 12, 13 and 14 C0.3 to v dd +0.3 v input voltage internal pull-up resistor C0.3 to v dd +0.3 v ports 12 to 14 openCdrain C0.3 to +7.3 v output voltage C0.3 to v dd +0.3 v one pin C15 ma all pins C30 ma peak value 30 ma one pin effective value 15 ma peak value 100 ma output current low effective value 60 ma peak value 100 ma total of ports 3 to 9 effective value 60 ma operating temperature storage temperature *1. when a voltage exceeding 6v is applied to ports 12, 13 and 14, the power supply impedance (pull-up resistor) should be 50k w or more. 2. effective value should be calculated: [effective value] = [peak value] duty note product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. operating voltage range cpu programmable threshold port (comparator input) other hardware C 40 + 60 c C 10 + 60 c C 40 + 60 c parameter test conditions min. max. unit h total of ports 0, 2, 12 to 14 47 m pd75116h,75117h capacitance (ta = 25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit c in c out 15 pf 15 pf input capacitance output capacitance input/output capacitance c io f = 1 mhz unmeasured pins returned to 0 v 15 pf oscillation circuit characteristics (ta = C40 to +60 c, v dd = 1.8 to 5.5 v) recommended test resonator parameter min. typ. max. unit constant conditions ceramic resonator after v dd reaches min. of oscillation voltage range crystal resonator external clock 2.0 5.0 *4 mhz 4ms 2.0 4.19 5.0 *4 mhz 10 ms 30 ms 2.0 5.0 *4 mhz 100 250 ns oscillator frequency (f xx ) oscillation stabilization time oscillator frequency (f xx ) oscillation stabilization time x1 input frequency (f x ) x1 input high-/low-level width (t xh , t xl ) x1 x2 m pd74hcu04 x1 x2 c1 c2 x1 x2 c1 c2 *5 *1 *1 *2 v dd = 4.5 to 5.5 v v dd = 2.7 to 5.5 v *2 *2 *3 *3 *1. when using in v dd < 2.7 v, the x2 pin oscillation waveform duty should be set within the range between 40% and 60%. t xxl t xxh v ss x2 oscillation waveform v dd 1 2 v dd duty = t xxl (or t xxh ) t xxl + t xxh ?100 2. oscillator frequency and x1 input frequency indicate oscillation circuit characteristics only. see ac characteristics for instruction execution time. 3. the oscillation stabilization time is the time required for oscillation to stabilize after v dd reaches min. of oscillation voltage range or the stop mode is released. 4. when the oscillator frequency is 4.19 mhz < f xx 5.0 mhz, pcc = 0011 should not be selected as the instruction execution time. if pcc = 0011 is selected, one machine cycle is less than 0.95 m s and the rated min. value of 0.95 m s is not observed. 5. the external clock cannot be used in v dd < 2.7 v. 48 m pd75116h,75117h note when the clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. the wiring should be kept as short as possible. no other signal lines should be crossed. keep away from lines carrying a high fluctuating current. the oscillator capacitor grounding point should always be at the same potential as v ss . do not connect to a ground pattern carrying a high current. a signal should be not taken from the oscillator. recommended oscillation circuit constant recommended ceramic resonator (ta = C40 to +60 c) external capacitance (pf) oscillation voltage range [v] manufac- turer frequency (mhz) 2.00 4.00 4.19 5.00 product name kbrC2.0ms pbrc 2.00a kbrC4.0msa pbrc 4.00a kbrC4.0mks kbrC4.0mws kbrC4.19msa pbrc 4.19a kbrC4.19mks kbrC4.19mws kbrC5.0msa pbrc 5.00a kbrC5.0mks kbrC5.0mws min. max. c1 47 33 iincorporated 33 iincorporated 33 iincorporated c2 47 33 iincorporated 33 iincorporated 33 iincorporated 1.8 5.5 kyocera 49 m pd75116h,75117h 0.7 v dd v dd v 0.8 v dd v dd v 0.8 v dd v dd v 0.7 v dd v dd v 0.8 v dd v dd v 0.7 v dd 6v 0.8 v dd 6v v dd C 0.5 v dd v v dd C 0.3 v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.2 v dd v 0 0.4 v 0 0.25 v v dd C 1.0 v v dd C 0.8 v v dd C 0.5 v v dd C 0.2 v 0.35 2.0 v 0.4 v 0.5 v 0.3 v 0.35 2.0 v 0.3 1.0 v 0.4 v 0.5 v 0.3 v 0.35 2.0 v 0.4 v 0.5 v 0.3 v 3 m a 20 m a 15 m a C3 m a C20 m a 3 m a 15 m a C3 m a 10 35 60 k w parameter symbol test conditions min. typ. max. unit dc characteristics (ta = C40 to +60 c, v dd = 1.8 to 5.5 v) internal pull-up resistor (mask option) output leakage current low output leakage current high r l i lol i loh2 i loh1 i lil2 i lil1 input leakage current low i lih3 i lih2 i lih1 other than below x1, x2 ports 12 to 14 (open-drain) other than below x1, x2 other than below ports 12 to 14 (open-drain) v in = v dd v iv = 6 v v in = 0 v v out = v dd v out = 6 v v out = 0 v ports 12 to 14 v ol v dd = 2.7 to 5.5 v v dd = 1.8 to 2.7 v v dd = 4.5 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 1.8 to 2.7 v i oh = C1 ma i oh = C100 m a v oh input leakage current high output voltage low x1, x2 v il3 ports 0,1,ti0, 1, reset other than below v il1 v dd = 2.7 to 5.5 v v dd = 1.8 to 2.7 v v dd = 2.7 to 5.5 v v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v v dd = 1.8 to 2.7 v v dd = 2.7 to 5.5 v v dd = 1.8 to 5.5 v ports 12 to 14 v ih4 x1, x2 v ih3 n-ch openC drain internal pull-up resistor ports 0,1,ti0, 1, reset v ih2 v ih1 other than below v dd = 2.7 to 5.5 v v dd = 1.8 to 2.7 v i ol = 15 ma i ol = 1.6 ma i ol = 400 m a i ol = 100 m a i ol = 15 ma i ol = 10 ma i ol = 1.6 ma i ol = 400 m a i ol = 100 m a i ol = 10 ma i ol = 1.6 ma i ol = 400 m a i ol = 100 m a v dd = 4.5 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 1.8 to 5.5 v v dd = 4.5 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 1.8 to 5.5 v v dd = 4.5 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 1.8 to 5.5 v ports 12 to 14 ports 3, 9 ports 0, 2, 4 to 8 output voltage high v il2 input voltage low input voltage high 50 m pd75116h,75117h dc characteristics (ta = C40 to +60 c, v dd = 1.8 to 5.5 v) v dd = 5 v 10 % *2 v dd = 3 v 10 % *2 v dd = 2 v 10 % *3 v dd = 5 v 10 % v dd = 3 v 10 % v dd = 2 v 10 % v dd = 5 v 10 % stop mode v dd = 3 v 10 % v dd = 2 v 10 % parameter symbol test conditions min. typ. max. unit 3.0 9.0 ma 1.6 4.8 ma 0.6 1.8 ma 0.7 2.1 ma 280 860 m a 120 360 m a 0.2 50 m a 0.1 20 m a 0.05 10 m a halt mode *1. excluding current flowing in the internal pull-up resistors and comparator circuit. 2. when the processor clock control register (pcc) is set to 0011 for operation in the high-speed mode. 3. when the pcc register is set to 0010 for operation in the low-speed mode. comparator characteristics (ta = C10 to +60 c*, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit v acomp v th v ipth compare accuracy threshold voltage pth input voltage comparator circuit current consump- tion pthm7 set to "1" * the comparator cannot operate in the range of ta = C40 to C10 c. it must be used within the range of ta = C10 to +60 c. v dd = 5.0 v v dd = 3.0 v v dd = 2.0 v 100 mv 0v dd v 0v dd v 0.7 ma 0.3 ma 0.1 ma supply current *1 4.19 mhz crystal oscillation c1 = c2 = 22 pf i dd1 i dd2 i dd3 51 m pd75116h,75117h 0.95 16 m s 1.91 16 m s 0 1 mhz 0 275 khz 0.48 m s 1.8 m s 0.8 m s 0.95 m s 3.2 m s 3.8 m s 0.4 m s t kcy /2 C 50 ns 1.6 m s t kcy /2 C 150 ns 0 300 ns 0 1000 ns v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.7 to 5.5 v input v dd = 4.5 to 5.5 v output input output input v dd = 4.5 to 5.5 v output input output v dd = 4.5 to 5.5 v ac characteristics (ta = C40 to +60 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit f ti t tih , t til t cy t ksi t sik t kso 100 ns 400 ns ti0, ti1 input frequency ti0, ti1 input high/ low-level width t kcy sck cycle time sck high/low-level width t kh , t kl si setup time (to sck ) si hold time (from sck ) so output delay time from sck ? int0 to int4 high/low-level width reset low-level width t inth , t intl t rsl 5 m s 5 m s cpu clock cycle time * (minimum instruction execution time = 1 machine cycle) 52 m pd75116h,75117h * the cpu clock ( f ) cycle time is determined by the oscillator frequency of the connected resonator and the setting of the processor clock control register (pcc). the graph on the right shows the characteristic for cycle time t cy supply current v dd during system clock operation. t cy vs. v dd supply voltage v dd [v] 012 3456 7 100 10 1.0 0.1 cycle time t cy [ s] m operating guarantee range ac timing test point (except ports 0, 1, ti0, ti1, x1, x2, reset) (1) v dd = 2.7 to 5.5 v 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd test points (2) v dd = 1.8 to 2.7 v 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points 53 m pd75116h,75117h clock timing (1) v dd = 2.7 to 5.5 v x1 input 1/f x t xl t xh v dd ?0.5 v 0.4 v (2) v dd = 1.8 to 2.7 v x1 input 1/f x t xl t xh v dd ?0.3 v 0.25 v ti0,ti1 input timing ti0, ti1 1/f ti t til t tih 0.8 v dd 0.2 v dd 54 m pd75116h,75117h sck input data output data t kso si so 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd t kcy t kh t kl t sik t ksi serial transfer timing interrupt input timing reset input timing t intl t inth int0?nt4 0.8 v dd 0.2 v dd t rsl reset 0.2 v dd 55 m pd75116h,75117h data memory stop mode low supply voltage data retention characteristics (ta = C40 to +60 c) parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v data retention supply current *1 i dddr v dddr = 2.0 v 0.05 10 m a release signal set time t srel 0 m s release by reset 2 17 /f xx ms t wait release by interrupt request *3 ms *1. excluding current flowing in the internal pull-up resistors and comparator circuit. 2. the oscillation stabilization wait time is the time during which cpu operation is stopped to prevent unstable operation when oscillation is started. 3. depends on the basic interval timer mode register (btm) setting (see table below). wait time btm3 btm2 btm1 btm0 (figures in parentheses are for operation at f xx = 4.19 mhz) 0 00 2 20 /f xx (approx. 250 ms) 0 11 2 17 /f xx (approx. 31.3 ms) 1 01 2 15 /f xx (approx. 7.82 ms) 1 11 2 13 /f xx (approx. 1.95 ms) stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait data retention timing (stop mode release by reset) oscillation stabilization wait time *2 56 m pd75116h,75117h stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request) data retention timing (standby release signal: stop mode release by interrupt signal) 57 m pd75116h,75117h n a m f b 48 49 32 k l 64 pin plastic qfp ( 14) 64 1 17 16 33 d c detail of lead end s q 55? p m i h j g p64gc-80-ab8-3 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 13. package information 64-pin plastic qfp ( 14) 58 m pd75116h,75117h 64-pin plastic qfp ( 12) h k j n a m f b 48 49 32 l 64 pin plastic qfp ( 12) 64 1 17 16 33 g detail of lead end s q 55 h d c p m i p64gk-65-8a8 item millimeters inches a b c d f g h i j k l 14.8 0.4 12.0 0.2 1.125 0.30 0.10 0.13 12.0 0.2 0.583 0.016 0.044 0.044 0.005 0.026 (t.p.) 0.472 note m n 0.10 0.15 1.4 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.055 0.008 0.012 0.472 0.6 0.2 0.024 p 1.4 0.055 0.583 0.016 14.8 0.4 1.125 +0.008 ?.009 q 0.1 0.1 0.004 0.004 s 1.7 max. 0.067 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 59 m pd75116h,75117h 14. recommended soldering conditions the m pd75117h should be soldered and mounted under the conditions recommended in the table below. for details of recommended conditions, refer to the information document "semiconductor device mount technology manual" (iei-1207) . for soldering methods and conditions other than those recommended below, contact our sales personnel. table 14-1 surface mount type soldering conditions (1) m pd75117hgc: 64-pin plastic qfp ( 14 mm) h recommended condition symbol soldering method soldering conditions package peak temperature : 230 c, duration : 30 sec. max. (at 210 c or avove), number of times : twice 60 m pd75116h,75117h item 4k/6k/8k/12k/16k 4k/8k 8k/12k/16k (mask rom) (mask rom) (mask rom) 320/320/512/512/512 320/512 512 rom (byte) ram ( 4 bits) m pd75104/106/108/112/116 m pd75104a/108a m pd75108f/112f/116f product name appendix a. functional differences among m pd751 series products 10 (pull-up resistor mask option : 4) 32 (pull-up resistor mask option : 24, led direct drive capability) 10 10 withstand voltage cmos input/output n-ch open-drain input/output cmos input total 12 (led direct drive capability *2 ) +12 v +10 v instruction set 75x high-end 58 analog input power-on reset circuit power-on flag on-chip (mask option) none 2.7 to 6.0 v C40 to +85 c C40 to +60 c pull-up resistor can be incorporated by mask option 4 (4-bit precision) operating temperature range 2.7 to 5.0 v (ta = C40 to +50 c) 2.8 to 5.0 v minimum instruction execution time 0.95 m s (operating at 4.5 to 6.0 v) 0.95 m s (operating at 4.5 to 5.0 v) 3.8 m s (operating at 2.7 v) 1.91 m s (operating at 2.7v) i/o port package *1. 75x high-end can also be used by means of the 16k-byte mode/24k-byte mode switching function. 2. for details, refer to the electrical specifications in each data sheet. operating voltage h 32 (led direct drive capability *2 ) 32 (led direct drive capability *2 ) ? 64-pin plastic qfp ( 14 mm) (resin thick 2.55 mm) ? 64-pin plastic qfp ( 14 mm) (resin thick 1.5 mm) ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) ? 64-pin plastic qfp (14 20 mm) 61 m pd75116h,75117h 16k/24k 8k 8k 24k (mask rom) (one-time prom, eprom) (one-time prom) (one-time prom) 768 512 768 75x high-end/extended 75x extended high-end high-end *1 58 10 m pd75116h/117h m pd75p108b m pd75p116 m pd75p117h 32 (led direct drive capability *2 ) 12 (led direct drive capability *2 ) +6 v +6 v can be incorporated by mask option none 4 (4-bit precision) none 1.8 to 5.5 v C40 to +60 c C40 to +85 c 2.7 to 6.0 v 5 v 10 % 1.8 to 5.5 v C40 to +60 c 0.95 m s (operating at 2.7 v) 1.91 m s (operating at 1.8 v) 0.95 m s (operating at 2.7 v) 1.91 m s (operating at 1.8 v) 0.95 m s (operating at 4.5 to 6.0 v) 3.8 m s (operating at 2.7 v) 0.95 m s (operating at 4.75 to 5.5 v) ? 64-pin plastic qfp ( 12 mm) ? 64-pin plastic qfp ( 14 mm) (resin thick 2.55 mm) ? 64-pin plastic shrink dip (750 mil) ? 64-pin ceramic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 20 mm) ? 64-pin plastic qfp ( 12 mm) ? 64-pin plastic qfp ( 14 mm) (resin thick 2.55 mm) 75x high-end +12 v 62 m pd75116h,75117h appendix b. development tools the following development tools are available for system development using the m pd75116h/75117h. ie-75000-r *1 ie-75001-r ie-75000-r-em *2 ep-75108agc-r ep-75117gk-r pg-1500 pa-75p117gc pa-75p117gk ie control program pg-1500 controller ra75x relocatable assembler 75x series in-circuit emulator emulation board for the ie-75000-r or ie-75001-r emulation probe for the m pd75116hgc/75117hgc. a 64-pin conversion socket (ev- 9200g-64) is also provided. emulation probe for the m pd75116hgk/75117hgk. a 64-pin conversion socket (ev- 9500g-64) is also provided. prom programmer prom programmer adapter for the m pd75p117hgc, connected to the pg-1500. prom programmer adapter for the m pd75p117hgk, connected to the pg-1500. host machines ? pc-9800 series (ms-dos? ver. 3.30 to ver. 5.00a *3 ) ? ibm pc/at? (pc dos? ver.3.1) ev-9200g-64 ev-9500g-64 software *1. maintenance product 2. not incorporated in the ie-75001-r. 3. a task swapping function is provided in ver. 5.00/5.00a, but this function cannot be used with this software. hardware 63 m pd75116h,75117h appendix c. related documents device related documents document name document number users manual iemC1340 instruction application table 75x series selection guide ifC1027 h document name document number ie-75000-r/ie-75001-r users manual eeuC1455 ie-75000-r-em users manual eeuC1294 ep-75117gk-r users manual eeuC1318 pg-1500 users manual eeuC1335 operation volume eeuC1346 language volume eeuC1343 pg-1500 controller users manual eeuC1291 development tools documents other documents document name document number package manual ieiC1213 surface mount technology manual ieiC1207 quality grade on nec semiconductor devices ieiC1209 nec semiconductor device reliability & quality control electrostatic discharge (esd) test semiconductor devices quality guide guarantee guide meiC1202 microcomputer related products guide other manufacturers volume note the information in these related documents is subject to change without notice. for design purpose, etc., be sure to use the latest ones. ra75x assembler package users manual hardware software 64 m pd75116h,75117h 65 m pd75116h,75117h ms-dos is a trademark of microsoft corporation. pc dos and pc/at are trademarks of ibm corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc. m4 92.6 m pd75116h,75117h |
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